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dm7300g series digital power manager data sheet zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 1 of 36 member of the family applications ? low voltage, high density systems utilizing dpwer tm digital intermediate bus architectures ? broadband, networking, optical, and wireless communications systems ? industrial computing, servers, and storage applicat ions benefits ? eliminates the need for external power management components ? communicates with the host system via the industry standard i2c communication bus ? reduces board space, system cost, complexity, and t ime to market features ? rohs compliant for all six substances ? compatible with both lead-free and standard reflow processes ? programs, controls, and manages up to 32 independen t dpol converters via an industry standard i2c interf ace (both 100khz and 400khz) ? jtag ieee 1149.1 compliant programming interface ? controls and monitors industry standard power suppl ies and other peripheral devices (fans, etc) ? programs output voltage, protections, optimal volta ge positioning, turn-on and turn-off delays and slew r ates, switching frequency, interleave (phase shift), and feedback loop compensation of the dpwer tm pol converters ? user friendly gui interface for programming, monito ring, and performance simulation ? four independent ok lines for flexible fault manage ment and fast fault propagation ? four interrupt inputs with programmable hot swap su pport capabilities ? intermediate bus voltage monitoring and protection ? ac fail input ? non-volatile system configuration data memory ? 1k byte of user accessible non-volatile memory ? control of industry standard dc-dc front ends ? crowbar output to trigger the optional crowbar prot ection ? run-time counter ? small footprint semiconductor industry standard qfn 64 package: 9x9mm ? wide industrial operating temperature range description power-ones point-of-load converters are recommende d for use with regulated bus converters in an inter mediate bus architecture (iba). t he dm7300 is a fully programmable digital power man ager that utilizes the industry-standard i 2 c communication bus interface to control, manage, pro gram and monitor up to 32 dp-series pol converters and 4 independent power devices. the dm7300 completely e liminates the need for external components for powe r management and programming and monitoring of the dp wer tm pol converters and other industry standard power and peripheral devices. parameters of the dm7300 a re programmable via the i 2 c bus and can be changed by a user at any time during product development and deployment. free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 2 of 36 1 selection chart dpm type number of dpwer tm pols and auxiliary devices that can be controlled active addresses number of groups number of interrupts number of parallel buses number of auxiliary devices dm7304g 4 00?03 2 2 2 4 dm7308g 8 00?07 2 2 4 4 dm7316g 16 00?15 3 3 4 4 DM7332G 32 00?31 4 4 8 4 2 ordering information dm 73 xx g ? yyyyy ? zz produ ct family: dpwer power management devices series: digital power manager number of dpwer tm pols and auxiliary devices: 04 ? 4 devices 08 ? 8 devices 16 ? 16 devices 32 ? 32 devices rohs compliance: g - rohs compliant for all six substances 5-digit identifier assigned by power-one for each unique configuration file packaging option 1) : b1 ? 50pcs tube b2 ? 10pcs tube r100 ? 100pcs t&r ______________________________________ 1 packaging option is used only for ordering and not included in the part number printed on the dpm labe l. 2 the evaluation board is available in only one confi guration: dm7300-kit-hks example: dm7316g-12345-r100 : a 100-piece reel of 16-node dpms with preloaded configuration file code 12345. each dpm is labeled dm7316g-12345. refer to figure 1 for la bel marking information. figure 1. label drawing d m73 xx g xxxxx x xxx xxxxxxx line 1 : part number (7 char. alpha numeric) line 2 : customer config. number, customer config. rev. (5 digits plus rev letter) line 3 : firmware rev. (3 char. alpha numeric) line 4 : programming (location, date, batch code) free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 3 of 36 3 standard 5-digit identifiers dpm type dpm preloaded with default configuration file dpm configured for jtag programming packaging options dm7304g 65511 65515 b1, b2, r100 dm7308g 65512 65516 b1, b2, r100 dm7316g 65513 65517 b1, b2, r100 DM7332G 65514 65518 b1, b2, r100 4 reference documents ? dp7xxx / dp8xxx point of load regulator data sheet s ? dm7300 digital power manager. programming manual, revision a09 or later ? graphical user interface, revision 6.3.5 or later ? programming dm7300 dpms via jtag interface. applic ation note ? zm00056-kit usb to i 2 c adapter kit. user manual free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 4 of 36 5 absolute maximum ratings stresses beyond those listed may cause permanent da mage to the dpm. exposure to absolute maximum rati ng conditions for extended periods may affect device r eliability. functional operation of the dpm at abs olute maximum ratings or conditions beyond those indicated in the operational sections of this specification is not implied. parameter conditions/description min max units ambient temperature range -40 85 c storage temperature (ts) -55 150 c junction temperature (t j ) 125 c input voltage vdd pin -0.3 3.6 vdc input voltage any pin other than vdd -0.5 vdd+0.5 vdc pin current dc 40 ma 6 mechanical specifications parameter conditions/description min nom max units peak reflow temperature 40 sec maximum duration 260 c lead plating 100% matte tin moisture sensitivity level jedec j-std-020c 3 7 reliability specifications parameter conditions/description min nom max units failure rate demonstrated at 55 c, 60% confidence level 2.26 fit non-volatile memory endurance -40c to 85c ambient 10,000 read- write cycles free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 5 of 36 8 electrical specifications specifications apply at vdd from 3v to 3.6v, ambien t temperature from -40c to 85c, and utilizing pro per decoupling as shown in figure 3 unless otherwise no ted. 8.1 power specifications parameter conditions/description min nom max units input supply voltage vdd pin 3.0 3.6 vdc undervoltage lockout hardware reset is triggered below this threshold 2.3 2.5 2.7 vdc input supply current vdd pin=3.3v 12 20 ma vref voltage aref pin 2.3 2.56 2.7 vdc ibvs input voltage range gnd vref vdc ibvs input resistance 100 m 8.2 feature specifications parameter conditions/description min nom max units intermediate voltage bus protections overvoltage protection threshold with external 5.7:1 ratio divider ibv 14.6 v undervoltage protection threshold with external 5.7:1 ratio divider 0 ibv v threshold hysteresis with external 5.7; 1ratio divider. symmetrical relative to average threshold value 114 mv accuracy of protection thresholds internal voltage reference, 1% resistive divider -10 10 %v th internal adc conversion error with external 5.7:1 ratio divider -43 43 mv front end enable (fe_en) v fe_en front end logic level enabled high v fe_en front end logic level disabled low isrc source current, v fe_en =v dd -0.5v 5 ma isink sink current, v fe_en =0.5v 5 ma crowbar (cb) v cb crowbar enable high v cb crowbar disable low isrc source current, v cb =v dd -0.5v 5 ma isink sink current, v cb =0.5v 5 ma t cb duration of enabling pulse 1 ms free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 6 of 36 8.3 signal specifications parameter conditions/description min nom max units sync/data line sdpu sd pull up resistor 5 k sdthrl sd input low voltage threshold 0.31vdd 0.52vdd v sdthrh sd input high voltage threshold 0.45vdd 0.81vdd v sdhys sd input hysteresis 0.37 1.1 v sdsink sd sink capability (v sd =0.5v) 30 ma freq_sd clock frequency 450 550 khz tsynq sync pulse duration 22 28 % of clock cycle t0 data=0 pulse duration 72 78 % of clock cycle interrupt inputs (int_n[3:0]) rpu3 pull up resistor 30 k vthrl3 input low voltage threshold 0.31vdd 0.52vdd v vthrh3 input high voltage threshold 0.45vdd 0.81vdd v vhys3 input hysteresis 0.37 1.1 v addr[3:0], acfail_n, res_n, lck_n, pg[3:0] inputs rpu1 pull up resistor 20 50 k vthrl1 input low voltage -0.5 0.2vdd v vthrh1 input high voltage 0.7vdd vdd+0.5 v hres_n input rpu2 hres_n pull up resistor (with series diode, see note 1) 30 60 k vthrl2 hres_n input low voltage -0.5 0.2vdd v vthrh2 hres_n input high voltage 0.9vdd vdd+0.5 v inputs/outputs (ok_a, ok_b, ok_c, ok_d) okpu ok pull up resistor 5 k okthrl ok input low voltage threshold 0.31vdd 0.52vdd v okthrh ok input high voltage threshold 0.45vdd 0.81vdd v okhys ok input hysteresis 0.37 1.1 v oksink ok sink capability (v ok =0.5v) 30 ma enable outputs (en[3:0]) v en en logic level enabled high v en en logic level disabled low v en h en output high voltage i oh = -10 ma vdd-0.6 v v en l en output low voltage i ol = 5 ma 0.5 v ______________________________________ 1 hres_n input - because the input does not have an i nternal esd protection diode connected to vdd, the user needs to add an external diode between the hres_n and vdd pins as shown in figure 3. free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 7 of 36 8.4 i 2 c interface parameter conditions/description min nom max units vil input low voltage -0.5 0.3vdd v vih input high voltage 0.7vdd vdd+0.5 v vhys input hysteresis 0.05vdd v vol output low voltage, i sink =3ma 0 0.4 v t r rise time for sda and scl 20+0.1c b 1 300 ns t of output fall time from vihmin to vilmax 20+0.1c b 1 250 ns ii input current each i/o pin, 0.1v dd zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 8 of 36 figure 2. i 2 c timing parameters 9 typical application figure 3. typical application schematic of multipl e output system with digital power manager and i 2 c interface the schematic of a typical application of a dm7300 digital power manager (dpm) is shown in figure 3. the system includes four groups of dpwer point of load convert ers (pols). a group is defined as one or more pol converters interconnected via ok pins. grouping of the pols e nables users to program advanced fault management s chemes and define margining functions, monitoring, startup behavior, and reporting conventions. all dpwer pol converters are connected to the dpm a nd to each other via a single-wire synchronization/ data (sd) line. the line provides synchronization of all pol converters to the master clock generated by the dp m and simultaneously carries bidirectional data transfer between pol converters and the dpm. the dpm commun icates via the i2c bus with the host system and/or the graphic al user interface. t r t lo w t hig h t lo w t hdst a t susta t hdda t t suda t t sust o t bu f t o f scl sda free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 9 of 36 in this application, besides pol converters, the dp m also controls and monitors two auxiliary devices C a voltage regulation module (vrm) and a low dropout regulator (ldo). while these devices are not dpwer complian t and may not even be manufactured by power-one, they are integrated into the system by communicating with t he dpm via their enable pins connected to enx outputs of t he dpm. in addition, the dpm monitors status of th e auxiliary devices via its pgx inputs connected to power good and error flag outputs of the auxiliary devices. t he dpm can control and monitor four or more independent auxili ary devices. the dpm can also trigger an optional crowbar circui t and provide undervoltage and overvoltage protecti ons of the intermediate bus voltage. in addition, the dpm can be controlled by a host system via the interrupt i nputs, res_n and the acfail_n inputs. 10 description the dm7300 series dpms perform translation between the i2c interface connected to a host system or the graphical user interface and the sd communication bus connect ed to dpol converters. in addition, dpms carry out programming, monitoring, data storage, pol group ma nagement, hot-swap control, protection, and control and monitoring of auxiliary devices. the dpms can be controlled via the gui or directly via the i2c bus by using specific commands describe d in the dpm programming manual. 10.1 dpm memory the dpm memory consists of ram and non-volatile mem ory (flash). the ram is used for programming opera tions and manipulation of the various blocks of configura tion, setup, status, and monitoring registers. non -volatile memory is used to store programming and configuration data . flash memory holds dpm set-up registers, pol set -up registers, monitoring data, and user memory data. s etup registers for the dpm and the pol converters a re protected by crcs that are checked during programming of pol converters and at the power-up of the dpm. the lck_n pin and the write protection register wp limit the write access to the memory blocks in the dpm and pol converters. the wp register content is default ed to write protect upon powering up the dpm. 10.1.1 write protection there are hardware-based and software-based memory write protections. the hardware protection takes p recedence over the software protection. 10.1.1.1 hardware protection the lck_n pin enables the hardware memory write pro tection. if the pin is pulled low, the hardware lo ck is active and the memory blocks are then read-only. i2c writ e commands to the dpm return an error code (0x00). the write commands to the pol converters bypassing the dpm ar e also disabled. if the pin is left floating, the hardware lock is disabled and the software write protection is activ e. 10.1.1.2 software protection software write protection allows users to protect t he various memory blocks from being overwritten thr ough the i2c bus. at the power-up the wp register is defaulted to write protect. software write protection can be disabled by checki ng appropriate boxes in the write protection subsec tion of the dpm/program/advanced dialog shown in figure 4 or vi a the i2c bus by writing directly into the register . write protections are automatically restored when the dpm s input power is recycled. free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 10 of 36 figure 4. gui dpm advanced programming dialog 10.1.2 dpm registers the dpm setup registers occupy 70 bytes and contain all necessary information to set up the dpm functi onality, define pol converters and auxiliary devices, group membership and behavior, margining, interrupt confi gurations, etc. they dpm registers are listed in. the table re lates to the dpm model number dm7332 capable of sup porting up to 32 pol converters. for other dpm models some of the registers and/or bits in the registers are not activated depending on the number of supported pols/groups/in terrupts/parallel buses for the specific dpm. writ ing into an unsupported register or bit will have no effect, reading from an unsupported register or bit will r eturn an error code (0x00). free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 11 of 36 table 1. dpm setup registers address offset 1 register name content register type user access write protect initial value 0x00 gd1[3:0] group definition register 1 static r /w yes 0x00000000 0x04 gd2[3:0] group definition register 2 static r /w yes 0x00000000 0x08 gac group a configuration static r/w yes 0x00 0x09 gbc group b configuration static r/w yes 0x00 0x0a gcc group c configuration static r/w yes 0x00 0x0b gdc group d configuration static r/w yes 0x00 0x0c fpc1 fault propagation configuration 1 static r/w yes 0x00 0x0d fpc2 fault propagation configuration 2 static r/w yes 0x00 0x0e epc error propagation configuration static r/ w yes 0x00 0x0f ic1 interrupt configuration 1 static r/w yes 0x00 0x10 ic2 interrupt configuration 2 static r/w yes 0x00 0x11 ibl[1:0] ibv low threshold static r/w yes 0x0 0 0x13 ibh[1:0] ibv high threshold static r/w yes 0x ff 0x15 id[1:0] dpm customer identification static ot p n/a 0xffff 0x17 pb1[3:0] parallel bus register 1 static r/w y es 0x00000000 0x1b pb2[3:0] parallel bus register 2 static r/w y es 0x00000000 0x1f pb3[3:0] parallel bus register 3 static r/w y es 0x00000000 0x23 pb4[3:0] parallel bus register 4 static r/w y es 0x00000000 0x27 pmc power manager configuration static r/w ye s 0x00 0x28 pid[31:0] pol identification register static r/w yes 0x00 0x80 rtc[3:0] run time counter run time r read only value at last shut-down 0x84 pps[3:0] pol programming status run time r (4 x) 0x00 0x88 est event status run time r 0x00 0x89 ibv[1:0] ib voltage run time r 0x00 0x8b sta status of group a run time r 0x00 0x8c stb status of group b run time r 0x00 0x8d stc status of group c run time r 0x00 0x8e std status of group d run time r 0x00 0x8f rel[1:0] dpm software release static r accor ding to dpm type 0x91 pss[3:0] pol status summary run time r 0x00 0x95 dpms dpm status run time r 0x01 0x96 wp write protection volatile r/w 0x00 ______________________________________ 1 writing into memory locations beyond address offset 0x96 must be avoided the static registers are saved in the non-volatile memory and used to store the system configuration d ata. the run- time registers contain status information and are e valuated during run-time. the write protection reg ister wp is a volatile register that defaults to write protect at power-up. 10.1.3 pol setup registers since the pol converters contain only ram, the data defining performance parameters for each pol and a uxiliary device, such as the output voltage, protection thre sholds, feedback loop compensation, turn-on and tur n-off delays, fault management settings, etc., is stored in the p ol setup registers in the dpm. the pol setup regis ters consist of 23 data bytes and 2 crc bytes. the auxiliary devic e setup registers occupy the same amount of bytes a s a pol converter, but only 3 registers have meaningful dat a. the other registers should be filled with 0x00. the pol setup registers are listed in table 2. register significa nce is different in some cases between the new dp a nd older zy series pols which are still supported. differences are in bold for the dp series devices. free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 12 of 36 table 2. pol setup registers address offset register +) content address offset register content dp7000 / dp8000 pol z7000 / z8000 pol aux device 00h pc1 _x protection configuration 1 00h pc1_x ec_x protection configuration 1 01h pc2_x protection configuration 2 01h pc2_x reserved protection configuration 2 02h pc3_x protection configuration 3 02h pc3_x reserved protection configuration 3 03h tc_x tracki ng configuration 03h tc_x reserved tracking configuration 04h int_x interleave configuration and frequency selection 04h int_x reserved interleave configuration and frequency selection 05h don_x turn - on delay 05h don_x eon_x turn - on delay 06h dof_x turn - off delay 06h dof_x eof_x turn - off delay 07h vlc voltage loop configuration 07h vos_x reserved output voltage set - point 08h cls_x current limit set - point 08h cls_x reserved current limit set - point 09h dcl_x duty cycle limit 09h dcl_x reserved duty cycl e limit 0ah pc4 protection configuration register 4 0ah b1_x reserved dig controller denominator z -1 coefficient 0bh v1h output voltage setpoint 1 high 0bh b2_x reserved dig controller denominator z -2 coefficient 0ch v1l output voltage setpoint 1 low 0c h b3_x reserved dig controller denominator z -3 coefficient 0dh v2h output voltage setpoint 2 high 0dh c0l_x reserved dig controller numerator z 0 coefficient low byte 0eh v2l output voltage setpoint 2 low 0eh c0h_x reserved dig controller numerator z 0 coe fficient high byte 0fh v3h output voltage setpoint 3 high 0fh c1l_x reserved dig controller numerator z -1 coefficient low byte 10h v3l output voltage setpoint 3 low 10h c1h_x reserved dig controller numerator z -1 coefficient high byte 11h cp controller proportional coefficient 11h c2l_x reserved dig controller numerator z -2 coefficient low byte 12h ci controller integral coefficient 12h c2h_x reserved dig controller numerator z -2 coefficient high byte 13h cd controller derivative coefficient 13h c3l_x reserved dig controller numerator z -3 coefficient low byte 14h cv controller derivative roll - off coefficient 14h c3h_x reserved dig controller numerator z -3 coefficient high byte 15h reserved 15h reserved reserved 16h reserved 16h reserved reserved 17h reserved 17h reserved reserved 18h reserved 18h reserved reserved 19h reserved 19h reserved reserved 1ah reserved 1ah reserved reserved 1bh reserved 1bh reserved reserved 1ch mrh margining high selection 1ch voml_x #) reserved output vo ltage margining low value 1dh mrl margining low selection 1dh vomh_x #) reserved output voltage margining high value 1eh crc0_x #) cyclic redundancy check register 0 1eh crc0_x #) crc0_x #) cyclic redundancy check register 0 1fh crc1_x #) cyclic redunda ncy check register 1 1fh crc1_x #) crc1_x #) cyclic redundancy check register 1 +) x denotes the pol address [0..31] #) not downloaded to the pol ______________________________________ x denotes the pol address [0..31] #) not downloaded to the pol during programming free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 13 of 36 10.1.4 monitoring data the dpms can retrieve current, temperature, output voltage, and status information from each of the po l converters and status information only from auxiliary devices. monitoring data is stored in ram and can be acces sed via the i2c bus. monitoring registers are read only. the monitoring data consists of 5 bytes for each po l converter and auxiliary device as shown in table 3. when the status monitoring is enabled, the st registers get continuously updated. when the parametric monitori ng is enabled, the voh, vol, io, and tmp registers get continuousl y updated. scaling data from the registers is speci fic to each dp and zy series pol. refer to the dm7300 programmi ng manual for calculation information. table 3: monitoring data registers pol converter auxiliary device register content register content st status register st status register voh output voltage high byte reserved vol output voltage low byte reserved io output current reserved tmp temperature reserved 10.1.5 user memory this non-volatile memory block is reserved for user s notes and not related to other functions in the dpm. it can be used to save user-specific information such as manu facturing data and location, serial number, applica tion code, configuration file version, warranty or repair info rmation, etc. a total of 1024 bytes organized in 4 pages is provided. the user memory can be accessed via the gui system configuration window shown in figure 8 or directly via the i2c bus using specific commands. content of the user m emory is saved into the configuration file when the file is saved. note that this does not change the current dpm cont ents until the dpm is programmed with the file curr ently in memory. free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 14 of 36 figure 5. user memory window 10.2 auxiliary devices the dm7300 dpm includes all necessary circuitry to control and monitor four auxiliary devices. virtua lly any device which has an on/off input and a monitoring output c an be an auxiliary device. typical examples of aux iliary devices include analog pol converters, linear regul ators, and fans. auxiliary devices are controlled and monitored via the graphical user interface. the dpm treats auxiliary devices as dpwer? pol conv erters: each auxiliary device has an address and is assigned to one of the groups as shown in figure 8 (device a t addresses 03). turn-on and off delays can be pro grammed, and faults can be propagated from pol converters to the devices. auxiliary devices are controlled through standard group turn-on and off commands and are fully synchr onized with turn-on/off timing of pol converters. four enable outputs en0en3 control the auxiliary d evices. four monitoring inputs pg0pg3 read status of the auxiliary devices. the enable outputs and monitori ng inputs are paired together and permanently assig ned to specific pins of the dpm as shown in figure 6. adding an aux device is done the same way as adding a pol, selec t an uncommitted address and then the aux device desired . in this example two aux devices are already prese nt. free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 15 of 36 figure 6. auxiliary device type window turn-on and turn-off delays can be programmed for e ach auxiliary device as shown in figure 7. timing of turn-on and turn-off events can be synchronized between aux iliary devices and pol converters by programming ap propriate delays for specific types of devices. figure 7. sequencing tracking window free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 16 of 36 10.3 dpm functions 10.3.1 pol programming pol programming is the process of downloading the c ontent of pol setup registers stored in dpms non-v olatile memory via the sd bus to the pol converters. programming of pol converters is performed upon pow er-up, or when the program button is pressed in the gui system configuration window shown in figure 8, or w hen the specific command is sent directly via the i 2c bus. figure 8. system configuration window the programming is performed in several steps. onc e the supply voltage on the vdd pins of the dpm exc eeds the uvlo protection threshold, the dpm will start copyi ng setup registers from its non-volatile memory int o ram and execute the cyclic redundancy check (crc) to ensure integrity of the programming data. when the volta ge on the ibvs pin exceeds the ibv undervoltage protection th reshold, the dpm will download pol setup registers to the respective pol converter via the sd line. every da ta transfer is protected by parity check and follow ed by the pol acknowledgement and read data back procedure. if b oth acknowledgement and readback operations are suc cessful, the pol-specific bit in the pol programming status registers will be set. the dpm considers the pol c onverter to be programmed, and continues programming the next p ol converter. upon completion of the programming, the dpm will tu rn-on the pol converters, if the auto turn-on is en abled in the pol group configuration window shown in figure 9 (topmost group of square buttons just below "bus voltages" tab. otherwise, the user will need to send the tur n-on command via the i2c bus. free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 17 of 36 figure 9. pol configuration window 10.3.2 programming time total system programming time can be determined fro m the following equation: ad ad pol pol init progr t n t n t t + + = where: t progr - time interval from the instant when the dpm supp ly voltage exceeds dpms uvlo threshold until the dpm issues the turn-on command. if the auto power- up is enabled, and the turn-on delay is set to zero , the output voltages start ramping up at the end of t progr interval t init - dpm initialization interval after the dpm supply voltage exceeds the uvlo threshold. t init =11.5ms. t pol - time required for programming and verifying of o ne pol converter. t pol =26.5ms. t ad - time required for programming and verifying of o ne auxiliary device. t ad =7.5ms. n pol - number of pol converters in the system. n ad - number of auxiliary devices in the system. free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 18 of 36 the programming data (dpm and pol setup registers a nd the user memory) can be preloaded into dpms by p ower- one or the dpms can be programmed by the user via t he gui, i2c bus, or jtag programming interface. th e dpms can be programmed either before or after insta llation on a host board. to modify pol converter settings, the user can dire ctly access the registers of a pol converter via th e i2c bus, bypassing dpms pol setup registers. the i2c comma nds are translated by the dpm and converted into ap propriate sd commands to read / write from / into the registe rs of a pol converter. writing into these register s is limited by the hardware (lck_n) and/or software write protecti ons. since pol converters do not have non-volatile memory, data written directly into pol converter registers will be lost when the input voltage is removed. 10.4 monitoring 10.4.1 pol monitoring dpwer tm and z-one? pol converters continuously monitor the ir own performance parameters such as output voltage, output current, and temperature. the moni tored parameters are stored locally in the pol conv erters and updated every 1ms. if monitoring feature is enable d, the dpm will be continuously copying status and parametric data from pol converters into dpms monitoring data regi sters. the monitoring is enabled by checking the appropria te retrieve monitoring bits in the gui group config uration window shown in figure 9 or directly via the i2c bu s by specific commands. if the status monitoring is enabled, the status of each protection (overcurrent, overvoltage, etc.) is being reported. if the parametric monitoring is enabled, then real-tim e values of voltage, current, and temperature are b eing reported. status and parametric monitoring data of a single p ol converter and groups of pol converters can be ex amined in the gui ibs monitoring window shown in figure 10 or directly via the i2c bus using specific commands. status data for each group of pol converters is presented in the group status block in the left top corner of the window. parametric data for individual pol converters is sh own in voltage [v], current [a], and temp [t] scree ns. dpms also monitor and report programming status of each pol converter and results of crc operations. 10.4.2 monitoring of auxiliary devices the dpm can read status information of the auxiliar y devices via the pg0pg3 inputs. the pg0pg3 are digital 3.3v compliant inputs with internal pull-up resisto rs. logic high input on a pgx pin should correspon d to normal operation of an auxiliary device. status monitoring data of auxiliary devices is stor ed in the dpm and displayed in the ibs monitoring w indow shown in figure 10. free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 19 of 36 figure 10. ibs monitoring window 10.4.3 run time counter the dpm also monitors the duration of time that it has been in operation. the 4 bytes run time counte r is active whenever the dpm is powered up. the count rate is 1 second. the counter is loaded into ram upon powe r-up and the new count state is periodically saved to the no n-volatile memory. contents of the counter can be examined in the gui ibs monitoring window shown in figure 10 or dir ectly via the i2c bus using specific commands. 10.4.4 ibv monitoring the dpm continuously monitors the intermediate bus voltage via the ibvs input and the built-in 10-bit adc. the digital representation of the bus voltage is stored in ram and reported in the ibs monitoring window s hown in figure 10. in addition, the dpm continuously compares the valu e of ibv to the undervoltage and overvoltage thresh olds programmed in the gui intermediate bus configuratio n window shown in figure 11. free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 20 of 36 figure 11. intermediate bus configuration window the thresholds have a symmetric, fixed size hystere sis as shown in figure 12 figure 12: undervoltage (ibl) and overvoltage (ibh) protections hysteresis when the ibv decreases below the ibl threshold minu s the hysteresis, the dpm will pull ok lines low tu rning off all pol converters. the pol converters will execute re gular turn-off ramping their output voltages down a ccording to the turn-off delay and falling slew rate settings. in addition, the dpm will clear all bits in the po l programming free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 21 of 36 status registers and save the content of the run ti me counter into the non-volatile memory. the ibv l ow bit in the ibs monitoring window will change to red. when the ibv recovers above the ibl threshold plus the hyst eresis, the dpm will first program all pol converters and then turn them on, if the auto turn-on is enabled in the pol group configuration window shown in figure 9. otherwise, the user will need to send the turn-on command via the i2c bus. when the ibv exceeds the ibh threshold plus the hys teresis, the dpm will pull ok lines low turning off all pol converters. the pol converters will execute regula r turn-off ramping their output voltages down accor ding to the turn-off delay and falling slew rate settings. in addition, the dpm will save the contents of the run time counter into the non-volatile memory. if the ibv does not decre ase below the ibh threshold minus the hysteresis wi thin the next 50ms, the dpm will pull low the fe_en output and cl ear all bits in the pol programming status register s. the ibv high bit in the ibs monitoring window will change t o red. if the ibv still does not change, in 50ms t he dpm will pull the cb pin high for 1ms to trigger an optional crowbar protection. one second after the ibv decreases below the ibh th reshold minus the hysteresis, the dpm will pull the fe_en high and program all pol converters. upon completi on of the programming process, the dpm will turn on the pol converters, if the auto turn-on is enabled in the p ol group configuration window shown in figure 9. the propagation delay between the ibv increasing/de creasing above/below corresponding thresholds and t he dpm pulling down ok lines and triggering the turn-off p rocess is approximately 1ms. 10.4.4.1 voltage reference for the purposes of ibv monitoring the user can sel ect either the dpms internal voltage reference or an external 2.5v voltage reference. the selection is made by c licking an appropriate radio button in the dpm conf iguration/bus voltages dialog as shown previously in figure 11 . he dpms internal 2.56v voltage reference guarantee s 10% overall accuracy of the ibv protection thresh olds. if the accuracy is sufficient, the user does not need to m ake any changes to the schematic shown in figure 3. if higher accuracy of the ibv monitoring is desired, then a 2 .5v external reference can be added as shown in fig ure 13. the gui automatically changes values of the ibl and ibh thresholds when the reference selection is changed . note: if the reference voltage setting is changed during operation of the dpm, then the power to the dpm ne eds to be cycled or the hres_n pin needs to be pulled low and releas ed figure 13. external voltage reference connections u1 and r1 are additional components. u1 is an indu stry standard 2.5v voltage reference such as tl431 or similar. c1 is an existing component but its value changes d epending on the type of voltage reference. common voltage reference part numbers and values of associated com ponents are shown in table 4. free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 22 of 36 table 4. component values for external reference u1 part number tl431 zr431 manufacturer ti zetex accuracy, % 0.5, 1, 2 0.5, 1, 2 r1, ohms 100-620 510-2000 c1, f 10 0.01 accuracy of the protection thresholds in the case o f external reference is determined by the sum of ac curacy of the voltage reference, accuracy of the 10k/47k resistiv e divider shown in figure 13, and conversion error of the internal adc specified in 8.2. 10.5 pol group management pol converters and auxiliary devices can be arrange d in up to four groups. a group of pol converters is defined as a number of pol converters with interconnected ok p ins. auxiliary devices are added to a group in the gui, without any external connections. a group can incl ude from 1 to 32 pol converters, but a pol converte r can be a member of only one group. in addition, the ok line s can be connected to the dpm to facilitate propaga tion of faults and errors between groups. one dpm can manage up t o four independent groups: a, b, c, and d, dependin g on model of the dpm. group management includes fault and error propagati on, margining, turn-on and turn-off, monitoring set up, and interrupt configuration. 10.5.1 fault and error propagation dp-series pol converters protect outputs by trigger ing either a fault or an error depending on the sev erity of the problem (see pol converter datasheets). fault prop agation between pol converters belonging to the sam e group is a programmable function of pol converters. the dpm a llows propagating faults and errors between groups of pol converters and, in case of an error, to a dc/dc fro nt-end and an optional crowbar. the propagation de lay for fault/error propagations is less than 10s. to enable fault and error propagation, the respecti ve bits needs to be checked in the gui fault and er ror propagation window shown in figure 14. note that cross propaga tion of faults/errors (means fault in group x propa gates to y and vice versa) should be avoided. free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 23 of 36 figure 14. fault and error propagation window. the fault propagation from pol converters to the au xiliary devices can be disabled by checking the bit in the auxiliary device fault management window as shown in figure 1 5. it is not possible to propagate a fault from an auxiliary device to pol converters. free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 24 of 36 figure 15. auxiliary device fault management windo w free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 25 of 36 table 5. fault and error propagation scenarios protection triggered propagation between pols propagation to auxiliary devices in the same group as the faulty pol propagation to auxiliary devices in other groups propagation between groups of pols faulty pol pols in the same group as the faulty pol auxiliary devices in the same group as the faulty pol pols in other groups auxiliary devices in other groups uvp or otp enabled disabled any disabled regular turn- off regular turn-off continue operating continue operating continue operating uvp or otp enabled enabled any disabled regular turn- off regular turn-off turn-off with turn- off delay continue operating continue operating uvp or otp enabled enabled disabled enabled regular turn- off regular turn-off turn-off with turn- off delay regular turn-off continue operating uvp or otp enabled enabled enabled enabled regular turn- off regular turn-off turn-off with turn- off delay regular turn-off turn-off with turn-off delay tracking or ocp enabled disabled any disabled fast turn-off regular turn-off continue operating continue operating continue operating tracking or ocp enabled enabled any disabled fast turn-off regular turn-off turn-off with turn- off delay continue operating continue operating tracking or ocp enabled enabled disabled enabled fast turn-off regu lar turn-off turn-off with turn- off delay regular turn-off continue operating tracking or ocp enabled enabled enabled enabled fast turn-off regul ar turn-off turn-off with turn- off delay regular turn-off turn-off with turn-off delay ovp or phase voltage enabled disabled any disabled fast turn-off, low side fet is on fast turn-off continue operating continue operating continue operating ovp or phase voltage enabled enabled any disabled fast turn-off, low side fet is on fast turn-off turn-off without turn-off delay continue operating continue operating ovp or phase voltage enabled enabled disabled enabled fast turn-off, low side fet is on fast turn-off turn-off without turn-off delay regular turn-off continue operating ovp or phase voltage enabled enabled enabled enabled fast turn-off, low side fet is on fast turn-off turn-off without turn-off delay regular turn-off turn-off with turn-off delay free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 26 of 36 when propagation is enabled, the faulty pol convert er pulls its ok pin low. a low ok line initiates t urn-off of other pol converters in the group and signals the dpm to pull other ok lines low to initiate turn-off of oth er pol converters as programmed. the regular turn-off of a pol converter means that the output voltage is ramping down according to its turn-off delay and falling slew rate settings. if a pol converter triggers an undervoltage or overtemperature fault, it will initiate the regular turn-off. in the case of an overcurrent or tracking fault, the pol converter initiates the fa st turn-off by opening both high and low side switches instantaneo usly. if either output overvoltage or phase voltag e errors are triggered, the faulty pol converter initiates the f ast turn-off and turns on its low side switch. in addition, when an error is propagated, the dpm can generate commands to turn off a front end (a dc-dc converter generati ng the intermediate bus voltage) and trigger an optional c rowbar protection to accelerate removal of the inte rmediate bus voltage (ibv). once the fault has recovered in the faulty pol conv erter, the other pol converters will turn on in a c ontrolled manner according to their turn-on delay and rising slew rate settings. 10.5.2 margining margining can be executed separately for each group by clicking an appropriate radio button in the gui ibs monitoring window shown in figure 10 or directly vi a the i 2 c bus by the margining command. all pol converters in a group are margined in the same direction (up or d own) by the percentage programmed individually for each pol converter. 10.5.3 turn-on and turn-off automatic turnCon upon application of the input vol tage is enabled by checking the auto turn-on bit in the gui group configuration window shown in figure 9. turn -on and turn-off of various groups during the opera tion is controlled from the gui ibs monitoring window or di rectly via the i 2 c bus by specific commands. 10.5.4 interrupt configurations the dpm has four interrupt inputs that can be progr ammed to: ? inhibit the operation of one or several groups of p ol converters when pulled low or ? act as a group reprogramming trigger. the two functions are mutually exclusive C an inter rupt can be either programmed as an inhibit or as a group reprogramming trigger. the interrupts are programmed in the gui interrupt configuration window shown in figure 16 or directly via the i2c bus by specific commands. in figure 16 the interru pt 0 is programmed as the inhibit for group a and t he interrupt 2 is programmed as the group c reprogramming trigger. 10.5.4.1 group inhibit an interrupt input can be programmed to act as an i nhibit on a single or multiple groups of pol conver ters. when the interrupt input is pulled low, the dpm will pul l the appropriate ok lines low. the affected pol c onverters will execute regular turn-off ramping their output volta ges down according to the turn-off delay and fallin g slew rate settings. once the interrupt is released, the pol converters will automatically turn-on according to their turn-on delay and rising slew rates settings. the inhibit function can be used for a variety of a pplications, such as ? hardware-based control of groups of pol converters and auxiliary devices free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 27 of 36 ? delayed turn-on at power-up (automatic turn-on is e nabled but the interrupts are held low during power-up. note that pol converters can be programm ed even when an interrupt is held low.) the interrupt inputs should be controlled with open collector devices. the propagation delay between the external device pulling the interrupt input low and the dpm pulling down ok lines and triggering the turn-off p rocess is approximately 10s. this option is set as part of d pm/configure/faults dialogs. figure 16. interrupt configuration dialog 10.5.4.2 group reprogramming trigger an interrupt that is programmed as a group reprogra mming trigger always acts only on one group of pol converters. interrupt 0 acts on group a, interrupt 1 acts on gr oup b and so on. the assignment is fixed and canno t be changed by the user. when the interrupt is pulled low, the dpm will prog ram the group of pol converters. upon completion o f the programming, the dpm will turn-on the pol converter s, if the auto turn-on is enabled. when the interr upt input is released, the dpm will pull the appropriate ok line low. the pol converters in the group will execute regular turn- off ramping their output voltages down according to the turn-off delay and falling slew rate settings. in addition, the dpm will clear all bits in the pol programming stat us registers. the group reprogramming trigger is mostly used to s upport hot swap of boards and daughter cards that d o not have a dpm installed on them as shown in figure 17. free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 28 of 36 figure 17: int0 configured as group a reprogramming trigger in this configuration the interrupt 0 (int0_n) is c onfigured as the group a reprogramming trigger. th e dpm is installed on a mother board or a backplane. a daug hter card with a group of pol converters is being i nserted in the system during normal operation. at first, the long pins carrying power and the ok_a line signal make contact. then the short pins carrying the sd and interrupt signal s make contact. once the interrupt senses low inpu t voltage, it will command the dpm to program all pol converters in th e group a. upon completion of the programming, the dpm will turn-on the pol converters, if the auto turn-o n is enabled. when the daughter card is being removed, the interr upt input is released as soon as the short pins bre ak the contact. the dpm will immediately pull the ok_a line low tur ning off all pol converters in the group a accordin g to the turn-off delay and falling slew rate settings. 10.6 controls 10.6.1 acfail_n and res_n the acfail_n and res_n are active low digital input s. when one of the inputs is pulled low, the dpm w ill pull all ok lines low turning off all the pol converters and the auxiliary devices in all groups. the pol conv erters will execute regular turn-off ramping their output volta ges down according to the turn-off delay and fallin g slew rate settings. in addition, the dpm will clear all bits in the pol programming status registers and save t he contents of the run time counter into the non-volatile memory. the ac_fail in or res_n in bit in the ibs monitori ng window will change to red. when the input is relea sed, the dpm will first program all pol converters and then turn them on, if the auto turn-on is enabled. otherwise , the user will need to send the turn-on command vi a the i2c bus. the acfail_n is typically connected to an ac-dc fro nt end. whenever the ac voltage disappears, the acfail_n signal will be set low. if there is no ba ttery backup, it usually means the dc output will d isappear after 20ms. if the turn-off delays and falling slew rate s of each pol converter are set to the values such that all pol converters will have fully turned off within the ho ld time of the ac-dc front end, then output voltage tracking during turn-off is guaranteed. the res_n input has the same functionality as the a cfail_n input and can be connected to a simple turn on/off switch or to a sensor that shuts the entire system down when it is activated. ibv gnd sd int 0 _ n ok _ a pol pol pol vox group a daugther card mother board or back plane dm 7300 sd free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 29 of 36 the acfail_n and res_n inputs should be controlled with open collector devices. the propagation delay between the external device pulling the input low and the d pm pulling down ok lines and triggering the turn-of f process is approximately 1ms. 10.6.2 front end enable the fe_en pin is dedicated to the control of a dc-d c front end. the front end is typically used to co nvert the 48v into the intermediate bus voltage (ibv). if th e dpm is powered from an auxiliary source, not from the ibv, it can control the dc-dc front end. when fe_en is internally pulled up to 3.3v, the fro nt end is enabled. the fe_en output can provide up to 5ma of current. when the fe_en goes low, the front end is disabled. the front end can be enabled and dis abled via the gui ibs monitoring window or directly via the i 2c bus using specific commands. the fe_en pin should not be directly connected to t he enable pin of the dc-dc front end. typically, t he enable pin is referenced to the primary side of the front end that is isolated from the low voltage secondary side. in addition, the enable pin can be pulled up internall y to a voltage potentially damaging to the dpm fe_e n output. the best method is to interface the dpm with the fr ont end through an optocoupler as shown in figure 1 8. this configuration provides interface for negative logic front ends. enable -vin r fe_en gnd q front end dpm r 3 . 3 k figure 18. interface between dpm and dc-dc front e nd 10.6.3 crowbar when the crowbar protection is enabled, the cb pin is internally pulled up to 3.3v for 1ms. it is cap able of supplying 5ma to turn on a crowbar circuit. 10.6.4 hres_n the hres_n is an active low digital input. when it is pulled low, the dpm will perform full hardware reset including processor, memory, and communication interface. th e pol converters and auxiliary devices will be turn ed off although sequencing and tracking during the turn-of f are not guaranteed. communication with a host pr ocessor or gui (if established) will be lost. when the input is released, the dpm will first program all pol con verters and then turn them on, if the auto turn-on is enabled. unlike all other i/o pins on the dm7300 dpm, the hr es_n does not have an internal esd protection diode connected to vdd. therefore, it is necessary to add the diode externally as shown in figure 3. the hres_n function is intended as an emergency res et and except as indicated below, should not be use d in normal system operation. free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 30 of 36 it is necessary to use an external reset circuit (see fig. 3) to h old the hres_n line low until the vdd supply reache s steady state conditions. power-one inc. successfull y tested the on-semi voltage detector p/n ncp303lsn 27t1 although other similar devices can also be utilized . alternatively, the hw_res pin can be connected to the output of a cpld (or similar device) and controlled via the sys tem supervisory circuitry. 10.7 communication interfaces 10.7.1 i 2 c interface the dm7300 series dpms have the industry standard i 2c interface fully meeting the requirements of the i2c -bus specification version 2.1 from philips semiconducto rs. the i2c interface is working in the following configurations: ? standard (100kbs) and fast (400kbs) data transfer r ates ? 7-bit addressing: 4 msbs fixed, 3 lsbs programmable by addr[2:0]. the address prefix of the dm7300 is 0x50. this allows encoding dpm addresses 0x50, 0x5 2, , 0x5e (bit0 is the read/write bit) the dpm always acts as the i2c slave while the host processor always acts as the i2c master. refer to the dpm programming manual for the detailed description of the i2c communications. note: it is recommended to use power-ones zm00056-kit u sb to i 2 c adapter kit for the communication between a dpm and a computer with the power-one i 2 cgraphical user interface 10.7.1.1 watchdog timer in order to prevent occasional hanging of the i2c b us, a watchdog timer is started whenever an i2c com mand is initiated. if the command is not executed before t he watchdog times out, the dpm will assume that the i2c bus is in an error condition (e.g. the scl or sda lines are p ulled low continuously) and it will reset the i2c b us. the watchdog timeout is 1000ms. since the watchdog function is not a part of the standard i2c specifications, it c an be disabled by the user. 10.7.2 jtag interface the dm7300 series dpms feature the jtag interface t hat can be used for programming the dpm with user-s pecific configuration settings. jtag boundary-scan capabil ities are not currently supported. jtag-programmable dpms have unique 5-digit identifi ers listed in table 6. table 6. jtag programmable dpm part numbers base part number 5- digit identifier dm7304g 65515 dm7308g 65516 dm7316g 65517 DM7332G 65518 only the dpm part numbers listed in the table can b e programmed via the jtag interface. note: the dpms can be programmed via the jtag only once. after initial programming via the jtag, the dpms may be reprogrammed via i 2 c as necessary 10.7.2.1 svf file free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 31 of 36 in order to program a dpm via the jtag interface, t he serial vector format (svf) file needs to be gene rated. click generate svf button in the system configuration win dow shown in figure 8. it will open the svf genera tor window shown in figure 19. the window allows specifying the location of the ta rget dpm in the jtag chain and setting delays to ge nerate the appropriate serial vector format file. the resulti ng file is used to program the dpms through the jta g interface. refer to programming dm7300 dpms via jtag interfac e application note for more details. figure 19. svf file generator window 10.7.2.2 jtag instructions dm7300 series dpms support only bypass and idcode i nstructions defined by ieee 1149.1. sample/preload and extest instructions are not curr ently supported. summary of the supported instructions is shown in table 7. table 7. jtag instructions instruction opcode register function bypass 1111 bypass places the 1-bit bypass register between the tdi an d tdo pins, which allows the bst data to pass synchronously thr ough the dpm to other devices in the jtag chain idcode 0001 jtag id selects the id register and pla ces it between the tdi and tdo note: the instruction register is 4-bit wide 10.7.2.3 identification register format and contents of the jtag identification regi ster are shown in table 8. free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 32 of 36 table 8. jtag id register msb lsb bit 31 28 27 12 11 1 0 description version part number manufacturer?s identity 1 contents 0000 1001010100000010 00000011111 1 free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 33 of 36 11 pinout table pin name pin no. pin type buffer type pin descripti on notes vdd 6, 25, 42, 57, 60 supply --- positive supply vss 8, 9, 26 38, 43, 58 supply --- ground sd 56 i/o st/ocpu sync-data line oka okb okc okd 11 13 20 53 i/o st/ocpu ok lines fe_en 17 o cmos front-end enable cb 23 o cmos crowbar trigger sda 30 i/o st/oc i 2 c interface scl 27 i/o st/oc i 2 c interface addr0 addr1 addr2 47 46 45 i stpu i 2 c interface address in0_n in1_n in2_n in3_n 41 40 37 36 i stpu interrupts tck tms tdo tdi 31 32 33 34 jtag interface leave open, if jtag interface is not utilized en0 en1 en2 en3 5 7 55 50 o cmos auxiliary device enables pg0 pg1 pg2 pg3 54 52 51 49 i stpu auxiliary device power good res_n 18 i stpu system soft reset acfail_n 16 i stpu ac-fail trigger lck_n 61 i stpu write protect lock hres_n 4 i stpu cold reset see important usage instructions in paragraph 10.6.4 ibvs 48 i a intermediate bus voltage sense aref 44 - a analog reference ir 63 internal reset connect to vss via 10k nc 1, 2, 3, 10, 12, 14, 15, 19, 21, 22, 24, 28, 29, 35, 39, 59, 62, 64 - - no connect leave floating legend: i=input, o=output, i/o=input/output, p=powe r, st=schmitt-trigger, ocpu=open collector with pul l-up, oc=open collector, cmos=cmos output stage, stpu=schmitt-trigger with p ull-up, a=analog free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 34 of 36 12 pins description acfail_n, ac fail input (pin 16): schmitt-trigger input with internal pull-up resistor (active low). pulling low the input indicates to the dpm that an ac-dc front- end has lost the mains and that a system shut down shou ld immediately be initiated. addr[0:2], i 2 c address inputs (pins 47, 46, 45): inputs with internal pull-up resistor. the 3 bit encoded address determines the dpm communication address for the i 2 c interface. aref, analog reference (pin 44): an analog reference which is used internally. a 10nf capacitor should be connected as close as possible to the package betwe en aref and vss. see 10.4.4.1. cb, crowbar output (pin 23): a cmos output which is used to trigger a crowbar (scr) in case of overvolt age on the intermediate voltage bus. en[0:3], enable outputs for auxiliary devices (pins 5, 7, 55, 50): cmos outputs to control auxiliary devices like linear regulators, analog pols, fans or other devic es. . fe_en, front-end enable (pin 17): a cmos output which is used to turn-on/off the dc/dc converter generating the ibv. hres_n, hardware reset (pin 4): input with internal pull-up resistor. when pulled low a cold start of t he digital power manager is initiated. refer to paragraph 10. 6.4 for important information regarding connections of this pin. ibvs, intermediate voltage bus sense (pin 48): analog input to an internal adc circuit to measure the intermediate bus voltage. the full scale range of the input is 2.56v and the ibv should be scaled down by a fac tor of 5.7 for proper reporting of the ibv with the dpwer? gui. int[0:3], interrupts (pins 41, 40, 37, 36): four active low inputs with internal pull-ups. each of the inputs can be configured for two functions: first, the interrupt input acts on the ok line(s) to stop momentarily the operation of group of pols and auxiliary devices, second the int errupt can be used as a hot swap trigger. in this functio n the interrupt input triggers the programming of a group . when released, pols are assumed to be disconnected from the dpm. ir, internal reset (pin 63): connect to vss via a 10kohm resistor. lck_n, memory lock (pin 61): active low input with internal pull-up. when lck_n is pulled low, all me mory within the dpm is write-protected. the write prote ction cannot be disabled by software. oka, okb, okc, okd, group ok signals (pins 11, 13, 20, 53): an open drain input/output with internal pull- up resistor. pulling low the ok input will indicat e to the dpm a fault in a group, the dpm can also pull an ok line low to disable a group. pg[0:3], power good (pins 54, 52, 51, 49): input with internal pull-up resistor. the pin is used to read the status of an auxiliary device. res_n, active low reset in/out (pin 18): input with internal pull-up resistor. when pulled low a soft reset of the system (sequenced turned off of all pols and auxili ary devices) is initiated. when released the whole sys tem is reprogrammed and started if necessary. sd, sync data line (pin 56): an open drain input / output with internal pull-up resistor. communicati on line to distribute a master clock to all converters and at the same time to communicate with all pols. jtag interface (pins 34, 33, 32, 31): connect to a jtag ieee-1149.1-compliant programmer supporting svf fil es or leave open, if not used. vdd, positive supply (pins 6, 25, 42, 57, 60): supply voltage. at least 4x100nf decoupling capacitors sh ould be connected between vdd and vss pins. all vdd pins must be connected. vss, ground (pins 8, 9, 26, 38, 43, 58): ground. decoupling capacitors need to be connected as close as possible to the pins. all vss pins must be connecte d. nc, no connect (pin 1, 2, 3, 10, 12, 14, 15, 19, 21 , 22, 24, 28, 29, 35, 39, 59, 62, 64): all nc pins must remain floating. free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 35 of 36 13 mechanical drawings figure 20. dm7300 mechanical drawing figure 21. dm7300 terminals mm inch min nom max min nom max a 0.80 - 1.00 0.032 - 0.040 j 0.0 0.01 0.05 0.000 0.002 a1 0.20 ref 0.008 ref d/e 9.00 bsc 0.354 bsc d1/e1 8.75 bsc 0.344 bsc d2/e2 4.50 4.70 4.90 0.177 0.185 0.193 n 64 p 0.24 0.42 0.60 0.009 0.016 0.024 e 0.50 bsc 0.020 bsc l 0.30 0.40 0.55 0.012 0.016 0.022 b 0.18 0.25 0.30 0.007 0.010 0.012 notes 1. compliant to jedec standard mo-220 variation vm md-3 free datasheet http:///
zd-00896 rev. 5.2, 9-apr-13 www.power-one.com page 36 of 36 figure 22. dm7300 mechanical drawing C top view 1. nuclear and medical applications - power-one pro ducts are not designed, intended for use in, or aut horized for use as critical components in life support systems, equipment used in hazardous environments, or nuclear control syste ms without the express written consent of the respective divisional president of p ower-one, inc. 2. technical revisions - the appearance of products , including safety agency certifications pictured o n labels, may change depending on the date manufactured. specifications are subject to change without notice. i 2 c is a trademark of philips corporation. free datasheet http:///

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